The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), which may be realized as metal oxide semiconductor field effect transistors (MOSFETs or MOS transistors). A MOS transistor may be realized as a p-type device (i.e., a PMOS transistor) or an n-type device (i.e., an NMOS transistor). Moreover, a semiconductor device can include both PMOS and NMOS transistors, and such a device is commonly referred to as a complementary MOS or CMOS device. A MOS transistor includes a gate electrode as a control electrode that is formed over a semiconductor substrate, and spaced-apart source and drain regions formed within the semiconductor substrate and between which a current can flow. The source and drain regions are typically accessed via respective conductive contacts formed on the source and drain regions. Bias voltages applied to the gate electrode, the source contact, and the drain contact control the flow of current through a channel in the semiconductor substrate between the source and drain regions beneath the gate electrode. Conductive metal interconnects (plugs) formed in an insulating layer are typically used to deliver bias voltages to the gate, source, and drain contacts.
A semiconductor device structure may include any number of active transistor regions, which are electrically isolated from one another using some form of isolation material, arrangement, or structures. For example, insulating material in the form of shallow trench isolation (STI) is commonly used to separate active semiconductor regions from each other. In practice, the creation of STI regions usually results in the formation of “divots” in the STI material. These divots are located where the STI meets the active silicon material. STI divots can be problematic in modern semiconductor device fabrication processes, particularly those that involve the use of high-k metal gate (HKMG) technologies.